This invention relates to a semiconductor memory device and more particularly to a semiconductor memory device utilizing a Metal-Insulator-Semiconductor (MIS) configuration.
In the prior art, a static type MIS memory for data storage is well known, wherein charge may be stored in the stray capacitance of a gate electrode of an MIS transistor. An MIS memory cell comprising even three or four MIS transistors generally has a simple configuration and requires less elements than a comparable device comprising bipolar transistors. The MIS memory cell occupies less area and accordingly higher integration density per chip can be obtained. However, the above MIS memory cell having three of four MIS transistors still occupies a considerably large area.
In view of the foregoing, a one transistor/cell type memory device has previously been developed. In the one transistor/cell type memory device, each memory cell is simply composed of one MIS transistor and one capacitor, and thus each memory cell occupies a small area. However, the above one transistor/cell type memory device has the following disadvantages. The reading of data is performed by detecting the rather small charge stored in the capacitor, which requires a sophisticated sense amplifier and complicated read-out procedures.